Photo of Chanyoung Moon

Chanyoung Moon

Undergraduate Student in Electrical Engineering, Korea University

I work on computer architecture and hardware-software co-design, with a focus on domain-specific accelerators.

I am an undergraduate in Electrical Engineering at Korea University. I spent 2025–26 as a visiting student at the University of Wisconsin-Madison and continue to work with Prof. Karu Sankaralingam in the Vertical Research Group. My first-author paper, FORGE (ASPLOS 2027), regenerates sparse MoE expert weights on chip instead of streaming them from HBM.

I am applying to Ph.D. programs for Fall 2027.

Education

Sep 2025 – May 2026

University of Wisconsin-Madison

Madison, WI

Visiting Exchange Student, Electrical and Computer Engineering

GPA: 3.94/4.0

Korea-U.S. Advanced Fields Youth Exchange ScholarMinister of Trade, Industry and Resources Award (1st of 213 scholars)

Mar 2021 – Aug 2027 (expected)

Korea University

Seoul, South Korea

B.E. in Electrical Engineering

GPA: 4.44/4.5 (Major: 4.46/4.5, Upper-division: 4.50/4.5)

Leave of absence for mandatory military service, Apr 2023 – Oct 2024

Publications

  1. ASPLOS 2027ConferenceFirst Author

    FORGE: Procedural Weight Generation for Sparse MoE Inference

    Chanyoung Moon, Travis Pence, Daisuke Yamada, Jiaqi Mo, Yanxin Zhang, Vikas Singh, Karthikeyan Sankaralingam

    ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2027

    An on-SM Rotor Generation Unit regenerates MoE expert weights on the fly, trading HBM weight traffic for on-chip computation. FORGE cuts parameter memory by 28–29% and raises system throughput by 1.3–2.8× at about 0.9% of GPU SM area (7 nm).

    arXiv

  2. NeurIPS 2026Conference

    Fast Sandwich Products in Clifford Algebra

    Travis Pence, Daisuke Yamada, Jiaqi Mo, Chanyoung Moon, Karthikeyan Sankaralingam, Vikas Singh

    Advances in Neural Information Processing Systems (NeurIPS), 2026

    A GPU kernel for the rotor sandwich product with bank-conflict-free shared-memory access, yielding up to 64× wall-clock and 35× memory improvements over existing implementations.

  3. IEIE Fall 2022Domestic ConferenceFirst Author

    Study for Behavior Verification and Resource Usage Analysis of RISC-V R-Type ISAs on FPGA

    Chanyoung Moon, Hyung Jin Cho, Junil Kim, Seon Wook Kim

    IEIE Fall Conference (Institute of Electronics and Information Engineers, Korea), 2022

News

  • Oct 2026 The FORGE (ASPLOS 2027) paper is now on arXiv.
  • Oct 2026 Gave lectures on GPU architecture at the HandS Architecture & System for AI Seminar, Korea University. Interactive lecture notes.
  • Sep 2026 First-author paper FORGE accepted to ASPLOS 2027.
  • Sep 2026 Fast Sandwich Products in Clifford Algebra accepted to NeurIPS 2026.
  • Sep 2026 Received the Minister of Trade, Industry and Resources Award, ranked 1st among 213 scholars of the Korea-U.S. Advanced Fields Youth Exchange Program.
  • Sep 2026 Selected for the NRF Undergraduate Research Fellowship (National Research Foundation of Korea).
  • Oct 2025 Joined the Vertical Research Group at UW-Madison, working with Prof. Karu Sankaralingam.
  • Sep 2025 Started a visiting exchange year at UW-Madison as a Korea-U.S. Advanced Fields Youth Exchange Scholar.

Research

I am interested in computer architecture, hardware-software co-design, and domain-specific accelerators. I look for structure that a workload has but the hardware-software interface discards, then add the minimal mechanism that exposes it.

Accelerators for LLM Inference

Trading memory traffic for on-chip compute: FORGE regenerates sparse MoE expert weights inside the SM instead of streaming them from HBM.

Sparse MoERTL designAccel-Sim

GPU Performance Analysis

Finding what limits a workload, on H100 and in cycle-level simulation, from shared-memory bank conflicts to serialized alpha blending.

CUDANsight Compute3D Gaussian Splatting

Real-Time System Co-design

Simulation-first design of closed-loop neural-machine interfaces, with the sensorimotor loop modeled as a multi-rate dependency graph under a sub-100 ms budget.

BCISystem simulationLatency budgets

Experience

Oct 2025 – Present

Vertical Research Group, University of Wisconsin-Madison

Madison, WI

Undergraduate Researcher, advised by Prof. Karu Sankaralingam

  • FORGE: Procedural Weight Generation for Sparse MoE Inference ASPLOS 2027

    • Project lead and first author.
    • Designed the Rotor Generation Unit (RGU), an on-SM accelerator that regenerates MoE expert weights from compact seeds to remove HBM weight traffic, raising system throughput 1.3–2.8× and cutting parameter memory 28–29% at about 0.9% GPU SM area (7 nm).
    • Exposed three axes of data parallelism in the generation algorithm and mapped them onto the RGU datapath; implemented and verified the RTL in SystemVerilog (cocotb, Verilator) and synthesized it for area and timing.
    • Built a system-level simulator to project end-to-end speedup, and later integrated the RGU into Accel-Sim for cycle-level GPU simulation.

  • Fast Sandwich Products in Clifford Algebra NeurIPS 2026

    Contributed to the GPU kernel for the rotor sandwich product with bank-conflict-free shared-memory access, enabling larger rotor-based layers with up to 64× wall-clock and 35× memory improvements over prior implementations.

  • Closed-Loop Neural-Machine Interface System Simulation Ongoing

    Leading a simulation-first BCI/exoskeleton co-design project. Building its simulator, which models the sensorimotor loop as a multi-rate dependency graph under a sub-100 ms budget to identify architectural bottlenecks.

  • 3D Gaussian Splatting Rendering Acceleration Ongoing

    Profiled GEMM-GS (DAC 2026) on H100. Showed that naive INT8 tensor-core quantization collapses PSNR (25.5 → 17.3) for only a 1.36× speedup, and identified true inter-Gaussian dependencies in alpha blending as the fundamental limit to further parallelization.

Sep 2026 – Present

Computer Systems Laboratory (CSL), Korea University

Seoul, South Korea

Undergraduate Researcher, Senior Thesis, advised by Prof. Jeongseob Ahn

  • Built a write-back, exclusive CPU-tier KV cache policy in vLLM to use scarce host DRAM efficiently in agentic LLM serving, raising throughput 21–30% over vLLM’s default when the CPU tier is 0.8–1.6× the GPU KV pool; developed an analytical recompute model that predicts throughput within 2% across 46 runs (preliminary).

Apr 2023 – Oct 2024

Defense Communication Command, Republic of Korea Army

Daejeon, South Korea

Microwave Communications Operator (Squad Leader)

  • Led a 10-member squad during mandatory military service; participated in two ROK-US combined forces exercises (UFS 2023, 2024).

Jul 2022 – Sep 2022

Compiler & Microarchitecture Lab (COMMIT), Korea University

Seoul, South Korea

Undergraduate Research Intern, advised by Prof. Seon Wook Kim

  • Designed a modular RISC-V R-type core in Verilog and verified 13 instructions on a ZedBoard FPGA; characterized its footprint (589 LUTs, 263 registers) as a baseline for sizing ISA extensions; first-authored a paper at the IEIE Fall Conference 2022.

Teaching

I am very interested in using AI to make hard concepts easy to understand. As AI builds things faster than ever, I think human understanding is becoming the main bottleneck, and interactive explainers like the one below are one way I am trying to address it.

Sep 2026 – Present

Architecture & System for AI Seminar, HandS Academic Society, Korea University

Co-host and lecturer

Co-hosted a weekly seminar for 21 students; lectured on GPUs, HBM, interconnects, and LLM serving.

Interactive lecture: Why Are GPUs Fast?

More explainers →

Honors & Awards

  • Minister of Trade, Industry and Resources Award 1st among 213 scholars, Korea-U.S. Advanced Fields Youth Exchange Program
    2026
  • NRF Undergraduate Research Fellowship National Research Foundation of Korea
    2026–2027
  • 3rd Korea-U.S. Advanced Fields Youth Exchange Scholarship Ministry of Trade, Industry and Resources, Republic of Korea
    2025–2026
  • Endowment Scholarship Awarded to the top student, School of Electrical Engineering, Korea University
    2025
  • Academic Excellence Scholarship Korea University, awarded for a 4.5/4.5 GPA (Spring 2022, Spring 2025, Fall 2025)
    2022–2025
  • Guwon Scholarship Foundation Award For academic excellence
    2022
  • Dean's Award Korea University, awarded for a 4.5/4.5 semester GPA (Fall 2021, Fall 2022, Spring 2025)
    2021–2025
  • Semester Highest Honors Korea University, 5 semesters
    2021–2025

Activities

  • Study Abroad Program, Korea Foundation for Advanced Studies (KFAS) One of 5 ECE students selected nationwide.
    Jun 2026 – Present
  • Young Engineers Honor Society (YEHS) Dean-recommended honor society of the National Academy of Engineering of Korea (NAEK).
    May 2025 – Present
  • Woonhwa Club, Korea University Vice President, 53rd cohort. Taught weekly science classes to 18 middle-schoolers from underserved households (144 hours) and raised over $10,000 in alumni sponsorship for the study room and club operations.
    Apr 2021 – Aug 2022

Contact

I am happy to talk about computer architecture, accelerator design, and ML systems.

cmoon27@wisc.edurchan02@korea.ac.kr